Embodiments of the invention relates to an array substrate and the manufacturing method thereof.
The technology of TFT-LCDs (Thin Film Transistor Liquid Crystal Displays) has been advancing rapidly during the past ten year; significant progresses have been made with respect to screen size and displaying quality, which puts TFT-LCDs in the trend of replacing CRTs.
The aperture ratio is an important factor of increasing LCD luminance and reducing power consumption; and using via holes of a half lap joint structure is one method of increasing the aperture ratio.
FIG. 1 is the schematic top view showing part of a traditional substrate. FIG. 2 is the side view of the section taken along A-A of FIG. 1.
As shown in FIG. 1 and FIG. 2, the array substrate comprises a base substrate 1, on which is formed a pattern comprising data lines 3 and gate lines 2 that crisscross one another, thus defining a plurality of pixel units. Beyond the area of the pixel units is the peripheral area, in which is formed the pattern of pad regions (interface regions), i.e., the data line pad regions 15 and the gate line pad regions 10 for respectively connecting the data lines 3 and the gate lines 2 to external driving circuits. In each pixel unit is provided a TFT switch and a pixel electrode 13; in particular the TFT switch comprises a gate electrode 4, an active layer 6, a source electrode 7, a drain electrode 8, and etc. Conductive patterns are kept insulated from each other by insulating materials. For example, the gate electrode 4 and the gate line 2 are covered by a gate insulating layer 5; and the data line 3, the active layer 6, the source electrode 7, and the drain electrode 8 are covered by a passivation layer 9. The pixel electrode 13 is connected with the drain electrode 8 via a drain electrode via hole in the passivation layer 9. To increase the aperture ratio of the pixel unit, the traditional half lap joint structure is used, in which the area of the drain electrode 8 is reduced, and the drain electrode via hole is provided on the edge of the drain electrode 8, i.e., a half of the drain electrode via hole is disposed on the edge of the drain electrode 8, and thus the via hole of the drain electrode 8 can also be referred to as the half lap joint via hole 11. In such a way, in the pixel electrode, part of the pixel electrode 13 is joined to the drain electrode 8, as shown in FIG. 1 and FIG. 2. It is usually necessary to provide a pad region via hole for a pad region, the material for the pixel electrode 13 is usually filled in the pad region, so as to protect the metal material of the pad region. The data line pad region 15 and the gate line pad region 10 do not have the issue regarding aperture ratio, the via holes in the data line pad region 15 and the gate line pad region 10 usually do not use the half lap joint structure, and thus they can be referred to as the full lap joint via holes 12.
The traditional manufacturing method, by using a mask, employs a method of continuously dry-etching the corresponding positions in the pixel unit after a full exposure to make the half lap joint via hole; the half lap joint structure is formed after the pixel electrode film is deposited.
It has been found that the above technique has the following defects: at the half lap joint structure, due to the dry etching, some of the gate scanning layer 5 below the drain electrode 8 is also etched away, which forms a cavity, as shown by the dashed circle area in FIG. 2. The cavity renders the structure vulnerable to layer discontinuity during deposing the pixel electrode 13 in the subsequent steps; and it renders the orientations of liquid crystal molecules near the cavity vulnerable to unpredictable deflections, which leads to light leakage. Moreover, the dangling part of the drain electrode 8 over the cavity is likely to fall off due to the later rubbing process, which forms impurity particles that adversely affect the displaying effect.